A high-tech enterprise focused on the R&D, design, production, packaging, testing and sales of computing, storage and compute-in-memory semiconductor chips. Founded in 2015, we serve AI computing power and high-security data infrastructure through our two core businesses — Lattice Computing and Secure Storage.
Shanghai NiceSemi Semiconductor Technology Co., Ltd. (NiceSemi) was founded in 2015, specializing in the R&D, design, production, packaging, testing and sales of computing, storage and compute-in-memory semiconductor chips.
Its subsidiary Jiangsu NiceSemi Semiconductor Co., Ltd. is located in Funing County, Jiangsu Province, with a plant area of 2,030 m², including a 1,000 m² Class-1000 cleanroom, providing memory chip packaging and testing capabilities.
The company is driven by two core businesses — Lattice Computing and Secure Storage — serving AI computing power and high-security data infrastructure needs.
Powered by Lattice Fabric / Extended PCIe + , this pioneering architecture achieves tight GPU/SSD coupling: GPUs and NVMe SSDs are directly paired through the extended PCIe interconnect, with end-to-end data exchange completed entirely within the expanded PCIe domain.
| Component | Specification / Function |
|---|---|
| Form Factor | Full-height full-length (FHFL) PCIe card, 312 × 111.15 mm, dual-slot thickness (with heatsink); optional E3.S backplane card form |
| PCIe Switch | Onboard high-lane-count PCIe Switch (64–96 lanes) that expands the PCIe domain, enabling extended PCIe interconnect |
| NVMe SSD Slots | 8 E3.S / U.2 (or M.2) NVMe SSD slots; each drive delivers ~100 GB/s over Gen6 x16, forming an SSD pool |
| GPU Interconnect Ports | PCIe x16 high-speed interface (cable/backplane) that connects external GPUs into the same PCIe domain for direct GPU↔SSD data exchange |
| Host Interface | PCIe x16 gold fingers connecting to the server CPU/motherboard |
| Power & Cooling | Auxiliary power (8-pin) + onboard VRM power module; large passive heatsink, optional active fan module |
| Software | KFNative™ driver & firmware: SSD pool discovery, KV-Cache mapping, Ring Reduce support |
Each GPU gets dedicated compute cache and KV-Cache; GPUs exchange data through direct links to adjacent SSDs, eliminating remote storage bottlenecks.
Traditional PCIe networks deliver millisecond-level latency; Lattice Interconnect achieves microsecond-level latency — an order-of-magnitude improvement that accelerates large-model inference and training.
Effective bandwidth increases by tens of times, fully resolving bandwidth bottlenecks and unleashing GPU compute power.
With All/All Ring Reduce support, training the largest-scale LLMs requires only 1/64 of the GPU count, dramatically cutting hardware costs.
Uses commercial GPUs without depending on NVLink, bypassing HBM and NVLink constraints to significantly reduce training costs and supply-chain risks.
175B parameters, 96 layers; Gen6 x16 SSD bandwidth of ~100 GB/s; each layer takes ~35 ms to load and ~180 ms to compute, running in an end-to-end pipeline.
World-leading precise sensing of devices' physical electromagnetic characteristics; each chip/hardware entity carries a unique "physical fingerprint" (PUF) ID — its one-of-a-kind identity; self-destruct on tampering: protects against disassembly, probing and chip reverse engineering.
Three generations of evolution: chip ID · anti-reverse → PCB ID · anti-disassembly → board-level system · anti-probing
Compliant with the ISO/IEC 20897-1 international standard; the world's only mass-produced, productized chip- and board-level physically unclonable tamper-proof IP core.
SATA 3.0 interface; protects core data assets and IP, prevents system counterfeiting, and enables rapid emergency destruction; can drop-in replace onboard NOR Flash chips.
Capacities of 32 GB / 64 GB / 128 GB; fully domestic and self-controlled (Fujian UMC + CXMT/YMTC NAND Flash); compatible with mainstream MLC/TLC flash; passes -60 °C stringent environmental testing; read/write performance of 400 MB/s; drop-in replacement for onboard eMMC.
World-leading needle-free stacked-die process; up to 32 memory dies per package, achieving TB-level capacity; package thickness DDP/DP ≤1.0 mm, ODP ≤1.2 mm, HDP ≤1.4 mm; staggered stacking + wire bonding.
Multiple chips are 3D-stacked and integrated into a single package, delivering multi-functionality / compact size / high performance / low power / high reliability; already in mass production; supports RF-front-end modularization.
CP Testing: Chroma 3380 + TEL P12 Prober; 8-inch / 12-inch wafers; three-temperature testing for memory and AI chips.
Automotive / Military Grade: Advantest 93000 series; automotive-grade three-temperature CP and automotive SMT module reliability testing.