Computing Storage Security NiceSemi

Shanghai NiceSemi Semiconductor Technology Co., Ltd.
NiceSemi

Science For Life

A high-tech enterprise focused on the R&D, design, production, packaging, testing and sales of computing, storage and compute-in-memory semiconductor chips. Founded in 2015, we serve AI computing power and high-security data infrastructure through our two core businesses — Lattice Computing and Secure Storage.

Lattice Computing Secure Storage
About Us

About Us

Shanghai NiceSemi Semiconductor Technology Co., Ltd. (NiceSemi) was founded in 2015, specializing in the R&D, design, production, packaging, testing and sales of computing, storage and compute-in-memory semiconductor chips.

Its subsidiary Jiangsu NiceSemi Semiconductor Co., Ltd. is located in Funing County, Jiangsu Province, with a plant area of 2,030 m², including a 1,000 m² Class-1000 cleanroom, providing memory chip packaging and testing capabilities.

The company is driven by two core businesses — Lattice Computing and Secure Storage — serving AI computing power and high-security data infrastructure needs.

R&D DesignProduction & PackagingSales & ServiceCompute PowerStorageCompute-in-MemorySecurity Protection
NiceSemi NiceSemi Lattice Computing Lattice Computing Secure Storage Security Storage Compute · Storage · Compute-in-Memory — Dual-Engine Driven AI Compute Power & High-Security Data Infrastructure
Lattice Computing

Lattice Computing — The Next-Generation AI Compute Architecture

KFNative™ · GPU/SSD Tight Coupling · Microsecond Latency · 10x Bandwidth

Definition in One Sentence

Powered by Lattice Fabric / Extended PCIe + KFNative™ , this pioneering architecture achieves tight GPU/SSD coupling: GPUs and NVMe SSDs are directly paired through the extended PCIe interconnect, with end-to-end data exchange completed entirely within the expanded PCIe domain.

Latency Comparison: Milliseconds → Microseconds

Traditional PCIe Networks — Millisecond-Level Latency

LatencyMillisecond-level

Lattice Interconnect — Microsecond-Level Latency

LatencyMicrosecond-level — an order-of-magnitude improvement

Lattice Interconnect PCIe Card

KF-6600 Mezzanine Edge Computing Card (PCIe Gen5 x16) — Product Photo
Note: The gold fingers plug into the server motherboard's PCIe slots; GPU interconnect ports bring external GPUs into the same PCIe domain via cables/backplanes, enabling tight GPU↔SSD coupling and microsecond-level data exchange.

Key Components & Specifications

ComponentSpecification / Function
Form FactorFull-height full-length (FHFL) PCIe card, 312 × 111.15 mm, dual-slot thickness (with heatsink); optional E3.S backplane card form
PCIe SwitchOnboard high-lane-count PCIe Switch (64–96 lanes) that expands the PCIe domain, enabling extended PCIe interconnect
NVMe SSD Slots8 E3.S / U.2 (or M.2) NVMe SSD slots; each drive delivers ~100 GB/s over Gen6 x16, forming an SSD pool
GPU Interconnect PortsPCIe x16 high-speed interface (cable/backplane) that connects external GPUs into the same PCIe domain for direct GPU↔SSD data exchange
Host InterfacePCIe x16 gold fingers connecting to the server CPU/motherboard
Power & CoolingAuxiliary power (8-pin) + onboard VRM power module; large passive heatsink, optional active fan module
SoftwareKFNative™ driver & firmware: SSD pool discovery, KV-Cache mapping, Ring Reduce support
Standard PCIe Card (Plug into Server) OCP 3.0 Accelerator Form E3.S Rack-Scale Backplane Integration GPU Server Companion Card

Technology Advantages

GPU/SSD Tight Coupling

Each GPU gets dedicated compute cache and KV-Cache; GPUs exchange data through direct links to adjacent SSDs, eliminating remote storage bottlenecks.

Microsecond-Level Latency

Traditional PCIe networks deliver millisecond-level latency; Lattice Interconnect achieves microsecond-level latency — an order-of-magnitude improvement that accelerates large-model inference and training.

Tens-of-Times Bandwidth

Effective bandwidth increases by tens of times, fully resolving bandwidth bottlenecks and unleashing GPU compute power.

1/64 GPU Count

With All/All Ring Reduce support, training the largest-scale LLMs requires only 1/64 of the GPU count, dramatically cutting hardware costs.

Bypass Restrictions

Uses commercial GPUs without depending on NVLink, bypassing HBM and NVLink constraints to significantly reduce training costs and supply-chain risks.

Performance Example: GPT-3 175B Inference

175B parameters, 96 layers; Gen6 x16 SSD bandwidth of ~100 GB/s; each layer takes ~35 ms to load and ~180 ms to compute, running in an end-to-end pipeline.

Three-Layer Technology Stack

Layer 1 · KV Cache · Vector Database Layer 2 · Native NVMe VM / Kubernetes Tier0 NFS(Tb/s IO & Networking) Layer 3 · Lattice PCIe Fabric All Flash Array
Three-layer decoupling: software-defined storage and compute at the top, native NVMe pass-through in the middle, and PCIe Fabric interconnect at the bottom — an end-to-end microsecond-level data path.
AI LLM Training / InferenceKV Cache AccelerationHPC High-Performance Computing GPU PoolingMemory PoolingBig Data Analytics VR/AR/RenderingNVMe SSD PoolingHigh-Performance Storage
Security Storage

Secure Storage — Tamper-Proof · Self-Controlled · Highly Reliable

NSVault™ · PUF 物理不可克隆 · 防破解存储 · 先进封装 · 全链路测试
NSVault™ Secure Storage eMMC 产品图
01 · PUF

PUF Physically Unclonable IP

World-leading precise sensing of devices' physical electromagnetic characteristics; each chip/hardware entity carries a unique "physical fingerprint" (PUF) ID — its one-of-a-kind identity; self-destruct on tampering: protects against disassembly, probing and chip reverse engineering.

Three generations of evolution: chip ID · anti-reverse → PCB ID · anti-disassembly → board-level system · anti-probing
Compliant with the ISO/IEC 20897-1 international standard; the world's only mass-produced, productized chip- and board-level physically unclonable tamper-proof IP core.

02 · sFlash

Tamper-Proof sFlash Secure Storage

SATA 3.0 interface; protects core data assets and IP, prevents system counterfeiting, and enables rapid emergency destruction; can drop-in replace onboard NOR Flash chips.

03 · eMMC

Tamper-Proof eMMC High-Capacity Secure Storage

Capacities of 32 GB / 64 GB / 128 GB; fully domestic and self-controlled (Fujian UMC + CXMT/YMTC NAND Flash); compatible with mainstream MLC/TLC flash; passes -60 °C stringent environmental testing; read/write performance of 400 MB/s; drop-in replacement for onboard eMMC.

04 · 3D Stacking

3D Stacking Packaging

World-leading needle-free stacked-die process; up to 32 memory dies per package, achieving TB-level capacity; package thickness DDP/DP ≤1.0 mm, ODP ≤1.2 mm, HDP ≤1.4 mm; staggered stacking + wire bonding.

Staggered Stacked Dies Substrate · Wire Bonding
05 · SiP

SiP System-in-Package

Multiple chips are 3D-stacked and integrated into a single package, delivering multi-functionality / compact size / high performance / low power / high reliability; already in mass production; supports RF-front-end modularization.

Testing Capabilities

CP Testing: Chroma 3380 + TEL P12 Prober; 8-inch / 12-inch wafers; three-temperature testing for memory and AI chips.
Automotive / Military Grade: Advantest 93000 series; automotive-grade three-temperature CP and automotive SMT module reliability testing.

FT Test Capacity8KK/month → 40KK/month
Module three-temperature testing · Capacity expansion in progress

Manufacturing & Testing Flow

Wafer Wafer Packaging 3D Stacking / SiP Testing CP / FT Three-Temperature
Wafer → color filter → packaging → testing: fully controlled production ensures the consistency, reliability and tamper-proof capability of secure storage chips.
Contact

Contact Us

Welcome to discuss cooperation on Lattice Computing and Secure Storage
Business Email
contact@nicesemi.tech
Company Address
No. 15 Hongqi Avenue, Funing County, Jiangsu Province